Power Supply Network Aware Timing Analysis Using S-parameter In Nanometer Digital Circuits
نویسندگان
چکیده
This paper describes a novel technique to analyze the effects of supply voltage noise on circuit delay for nanometer VLSI circuits. Scattering parameters are used to analyze the power supply noise and to reduce runtime and memory usage. The interconnections of the power grid are modeled by RLC passive elements, constant voltage and time-varying current sources. A fast and accurate MOS modeling method for static timing analyzer is proposed based on the power grid analysis. MOS is modeled in three different regions during transition, and the maximum delay is formulated as a constrained non-linear optimization problem by considering the power supply noise (inclusive of the IR-drop and the Ldi/dt drop). The proposed technique has been applied to ISCAS85 benchmark circuits redesigned in 45nm technology. The results are compared to Hspice; they show that the error is within 5% of the Hspice simulation results. Index Terms IR-Drop, Ldi/dt, Power Supply Network, Power Supply Variation, Timing Variation, Cell Characterization.
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